The escalating demands of high-performance computing (HPC) systems, driven by intensive computational needs, have led to increased power consumption and heat generation, posing thermal challenges that limit system performance. The adoption of advanced packaging technologies like 2.5D, 3D, and heterogeneous integration further complicates cooling in HPC applications. Traditional methods such as air cooling and immersion prove inadequate, sparking increased interest in liquid cooling first demonstrated in 1981. Research, notably influenced by DARPA's ICECOOL program, has explored various liquid cooling methods such as backside-of-die and micro cooler-bonded systems, using different architectures and fluids. Most research modified packaged chips, with limited instances of wafer-level fabrication of micro coolers. The report highlights the need to explore wafer-level approaches, emphasizing their potential to mitigate processing challenges and reduce risks. It outlines key considerations for chip-based micro cooling integration in HPC systems, drawing insights from a SEMI-convened committee to recommend the next steps for transitioning these cooling technologies into production.
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• Review of advanced packaging approaches utilized in HPC applications, including heterogenous integration, 2D/2.5D/3D chip packaging architectures, and combinations of these arrangements
• Summary of reported results of on-chip cooling research, focusing on microchannel cold-plates and microchannels etched into die
• Key process technologies required for creating microchannels, and the maturity of each
• A proposed thermal test vehicle for evaluating commercial implementation of microchannels is described
• Key issues are identified, and suggestions for next steps, in particular, the CHIPS for America’s National Advanced Packaging Manufacturing Program (NAPMP) is identified as an opportunity for collaborative development among the HPC supply chain